| Are you designing IC's? You surely don't do this on your own. Normally, your employer has the required documentation.
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A clock period delay is implemented with delay-lines. Usually an RC circuit - which can be on the chip itself, but it can also be external (a real physical wire of a specific length will do the job too). You need a lot of mathematical skills to design this.
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clock period delays are needed to keep all logic elements synchronized. As the slowest circuits cannot be accelerated, the fastests are slowed down - with delays. | 
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